1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor device structures. More particularly, the present invention relates to a method for creating depressions in a semiconductor substrate or film using laser machining processes and using such depressions for defining precise electrical pathways in a semiconductor device structure.
2. Background of the Related Art
Connection lines (e.g., lead and/or bond connections), traces, signals and other elongated conductive elements are utilized in semiconductor device structures to carry electronic signals and other forms of electron flow between one region of the semiconductor device structure and another and between regions within the semiconductor device structure and external contacts (e.g., solder balls, bond pads and the like) associated therewith. Conventional methods for forming such elongated conductive elements utilize a damascene process wherein one or more depressions is etched in a semiconductor substrate or film, backfilled with an electrically conductive material and polished back or “planarized” even with the surface of the substrate or film. As used herein, the term “depression” includes troughs, channels, vias, holes and other depressions in and through a semiconductor substrate or film, which depressions may be used to define electrical pathways that carry electronic signals between one region of a semiconductor device structure and another, and between regions within the semiconductor device structure and external contacts associated therewith, as well as providing power, ground and bias to integrated circuitry of the semiconductor device structure. Such electrical pathways may include, without limitation, the depressions used to define traces or lines for signal lines, power and ground lines, and the like.
FIGS. 1A-1E schematically depict a conventional damascene process sequence for creating elongated conductive elements in the form of traces 26 in an interlevel dielectric layer 14. It will be understood by those of ordinary skill in the art that while the process depicted illustrates formation of a plurality of traces 26, the process sequence is typically utilized for the formation of other elongated conductive elements, e.g., lines for signal lines, power and ground lines, as well. It will be further understood that the methods and structures described herein do not form a complete process for manufacturing semiconductor device structures. The remainder of the process is known to those of ordinary skill in the art and, therefore, only the process steps and structures necessary to understand the conventional process sequence are described herein.
Referring to FIG. 1A, a cross-sectional view of a first intermediate structure 10 in the fabrication of a semiconductor device structure 24 having a plurality of traces 26 in the interlevel dielectric layer 14 thereof is illustrated. The first intermediate structure 10 includes an interlevel dielectric layer 14, e.g., thermally grown silicon dioxide (SiO2), which resides on a semiconductor substrate 12, such as a silicon wafer. It should be understood by those of ordinary skill in the art that the figures presented in conjunction with this description are not meant to be actual cross-sectional views of any particular portion of an actual semiconductor device, but are merely idealized representations which are employed to more clearly and fully depict the conventional process sequence than would otherwise be possible. Elements common between the figures maintain the same numeric designation.
A photoresist layer 16, formed from a conventional photoresist material, is disposed atop the interlevel dielectric layer 14 and one or more trace precursors in the form of trace depressions 18 are patterned in the photoresist layer 16 using conventional photolithography techniques. The patterned trace depressions 18 may be of any shape or configuration including, but not limited to, circles, ovals, rectangles, elongated slots and the like.
As shown in FIG. 1B, the interlevel dielectric layer 14 is subsequently etched using the photoresist layer 16 as a mask so that the patterned trace depressions 18 are extended into the interlevel dielectric layer 14. Such etching processes are known to those of ordinary skill in the art and may include, without limitation, reactive ion etching (RIE) or an oxide etch. As shown in FIG. 1C, the photoresist layer 16 is subsequently removed by a conventional process, such as a wet-strip process, a tape lift-off technique, or combinations thereof, creating a second intermediate structure 20.
As shown in FIG. 1D, an electrically conductive material 22, e.g., tungsten, is subsequently blanket deposited over the interlevel dielectric layer 14 such that the trace depressions 18 are filled therewith. The electrically conductive material 22 is then planarized using, e.g., a mechanical abrasion technique, such as chemical mechanical planarization (CMP), to isolate the electrically conductive material 22 in the trace depressions 18, as illustrated in FIG. 1E. Thus, a semiconductor device structure 24 including a plurality of traces 26 in the interlevel dielectric layer 14 thereof is fabricated.
For more complex electrical pathways, for instance, those in which both an elongated conductive element (e.g., a trace) and one or more discrete conductive structures (e.g., vias) are to be defined in a single interlevel dielectric layer, a dual damascene process may be utilized. FIGS. 2A-2I illustrate a conventional dual damascene process sequence. Referring to FIG. 2A, a cross-sectional view of a first intermediate structure 10′ in the fabrication of a semiconductor device structure 24′ having a plurality of traces 26′ and a plurality of conductor-filled vias 32 in the interlevel dielectric layer 14′ thereof is illustrated. The first intermediate structure 10′ includes an interlevel dielectric layer 14′, e.g., thermally grown SiO2, which resides on a semiconductor substrate 12′, such as a silicon wafer. A mask layer 28 having a plurality of trace precursors in the form of trace depressions 18′ patterned therein, is disposed atop the interlevel dielectric layer 14′. The patterned trace depressions 18′ may be of any shape or configuration including, but not limited to, circles, ovals, rectangles, elongated slots and the like.
As shown in FIG. 2B, a photoresist layer 16′, formed from a conventional photoresist material, is subsequently deposited atop the mask layer 28 such that the patterned trace depressions 18′ are filled therewith. Next, as shown in FIG. 2C, conventional photolithography is performed on the photoresist layer 16′, thereby forming a patterned photoresist layer 16″ having a plurality of vias 30 patterned therein which align with the trace depressions 18′ of the mask layer 28.
Referring to FIG. 2D, the interlevel dielectric layer 14′ is subsequently etched, using, e.g., RIE, utilizing the patterned photoresist layer 16″ as a mask. The pattern of vias 30 is accordingly extended into the upper portion of the interlevel dielectric layer 14′.
As shown in FIG. 2E, the patterned photoresist layer 16″ is subsequently removed, forming a second intermediate structure 20′. Thereafter, the interlevel dielectric layer 14′ is etched using the mask layer 28 with the patterned trace depressions 18′ therein and the upper portion of the interlevel dielectric layer 14′ with the vias 30 therein as a mask. This step is shown in FIG. 2F. As a result, the desired trace pattern is extended into the upper portion of the interlevel dielectric layer 14′ and the vias 30 in the upper portion of the interlevel dielectric layer 14′ are concurrently extended into the lower portion of the interlevel dielectric layer 14′.
Subsequently, as shown in FIG. 2G, the mask layer 28 is removed by a conventional process creating a third intermediate structure 34. An electrically conductive material 22′, e.g., tungsten, is then blanket deposited over the interlevel dielectric layer 14′ such that the trace depressions 18′ and vias 30 are filled therewith, as shown in FIG. 2H. The electrically conductive material 22′ is then planarized using, e.g., a mechanical abrasion technique such as chemical mechanical planarization (CMP), to isolate the electrically conductive material 22′ in the vias 30 and trace depressions 18′. This step is illustrated in FIG. 21. Thus, a semiconductor device structure 24′ having a plurality of traces 26′ and a plurality of conductor-filled vias 32 defined in a single interlevel dielectric layer 14′ thereof is fabricated.
Further methods of forming damascene and dual damascene structures are known. For instance, U.S. Pat. No. 6,495,448 describes an additional process for forming a dual damascene structure. However, all such conventional methods include one or more photolithography processing steps which significantly impact the cost of manufacturing semiconductor device structures. Further, elongated conductive elements, such as traces, and discrete conductive structures, such as vias or bond pads, must be created during separate and distinct processing steps, again increasing the cost and complexity of manufacture. Still further, such techniques, while effective for forming elongated conductive elements and discrete conductive structures in the material for which the technique was designed, e.g., SiO2, may not be as effective for creating such conductive elements or structures in other materials, such as semiconductor substrates (e.g., silicon wafers) or films (e.g., passivation films).
Accordingly, the inventor has recognized that a method of forming elongated conductive elements and discrete conductive structures in a semiconductor substrate or film that utilizes fewer process steps and less material than conventional processing techniques would be desirable. Further, the inventor has recognized that a method of forming elongated conductive elements and discrete conductive structures which is void of photoprocessing steps and which may be utilized to create multiple elongated conductive elements and discrete conductive structures substantially simultaneously would be advantageous.
Laser machining of interconnects for external contacts and of conductive vias is known in the art. For instance, in U.S. Pat. No. 6,107,109, a method for fabricating a straight line electrical path from a conductive layer within a semiconductor device to the backside of a semiconductor substrate using a laser beam is disclosed. The method includes forming an opening through a substrate to electrically connect external contacts engaged on a face side thereof to the backside of the substrate. The opening is perpendicular to both the face side and backside of the substrate. In one embodiment, the openings are formed using a laser machining process.
U.S. Pat. No. 6,114,240 discloses a method for laser machining conductive vias for interconnecting contacts (e.g., solder balls, bond pads and the like) on semiconductor components. In the described method, a laser beam is focused to produce vias having a desired geometry, e.g., hourglass, inwardly tapered, or outwardly tapered.
The inventor has recognized that a laser machine processing technique which may be used for the formation of elongated conductive elements, e.g., traces and the like, in semiconductor substrates or films would be advantageous. Further, a technique wherein multiple and different elongated conductive elements and discrete conductive structures may be defined in a single layer (e.g., a substrate or film) substantially simultaneously would be desirable.